Digital Electronics and Computer Organization
UNIT-I: Logic Gates and Circuit
Gates (OR, AND, NOR, NAND, XOR & XNOR); Demogran’s laws; Boolean laws, Circuit designing techniques (SOP, POS, K-Map).
UNIT-II: Combinational Building Blocks
Multiplexes; Decoder; Encoder; Adder and Subtracter.
UNIT-III: Memories
ROMs, PROMs, EPROMs, RAMs, Hard Disk, Floppy Disk and CD-ROM.
UNIT-IV: Sequential Building Blocks
Flip-Flop (RS, D, JK, Master-slave & T flip-flops); Registers & Shift registers; Counters; Synchronous and Asynchronous Designing method.
UNIT-V: Memory Organization
Basic cell of static and dynamic RAM; Building large memories using chips; Associative memory; Cache memory organisation and Virtual memory organisation.

UNIT-I: Logic Gates and Circuit

1. Logic Gates

Logic gates are the basic building blocks of digital electronics. Each gate performs a specific logical operation on one or more inputs to produce an output.

Common Logic Gates:

Example Truth Table: XOR Gate

    A | B | A ⊕ B
    -------------
    0 | 0 |  0
    0 | 1 |  1
    1 | 0 |  1
    1 | 1 |  0
            

Diagram:

[Illustration of each logic gate symbol – can be added as images if required]

2. De Morgan’s Laws

These laws are used to simplify expressions in Boolean algebra.

Example:

    Given: (A + B)'
    Apply: A' ⋅ B'
    So, (A + B)' = A' ⋅ B'
            

3. Boolean Laws

These are rules used to simplify Boolean expressions.

Example Simplification:

    Expression: A + AB
    Apply: A(1 + B) = A ⋅ 1 = A
    Final Answer: A
            

4. Circuit Designing Techniques

1. SOP (Sum of Products)

SOP is the sum (OR) of multiple product (AND) terms.

    Example: F = A'B + AB'
            

2. POS (Product of Sums)

POS is the product (AND) of multiple sum (OR) terms.

    Example: F = (A + B)(A' + C)
            

3. K-Map (Karnaugh Map)

K-Map is used to simplify Boolean expressions by organizing them into a table format.

Example for 2 variables:

    | A | B | Output |
    |---|---|--------|
    | 0 | 0 |   0    |
    | 0 | 1 |   1    |
    | 1 | 0 |   1    |
    | 1 | 1 |   0    |
    
    This is XOR logic. K-map grouping simplifies to A'B + AB'
            

Diagram:

[Draw K-map grids and groupings – image or diagram can be inserted]

UNIT-II: Combinational Building Blocks

1. Multiplexer (MUX)

A multiplexer selects one input from multiple inputs and forwards it to the output using selection lines.

Example: 4-to-1 Multiplexer

      Inputs: I0, I1, I2, I3
      Select lines: S0, S1
      Output: Y = I0.(S1'.S0') + I1.(S1'.S0) + I2.(S1.S0') + I3.(S1.S0)
          

Truth Table:

      S1 | S0 | Output (Y)
      --------------------
       0 |  0 |   I0
       0 |  1 |   I1
       1 |  0 |   I2
       1 |  1 |   I3
          

Diagram:

[Block diagram of 4-to-1 MUX with 4 inputs, 2 selection lines, and 1 output]

2. Decoder

A decoder converts binary data from 'n' input lines to a maximum of 2ⁿ unique output lines.

Example: 2-to-4 Decoder

      Inputs: A0, A1
      Outputs: Y0 to Y3
      Y0 = A1'.A0' ; Y1 = A1'.A0 ; Y2 = A1.A0' ; Y3 = A1.A0
          

Truth Table:

      A1 | A0 | Y3 Y2 Y1 Y0
      ---------------------
       0 |  0 |  0  0  0  1
       0 |  1 |  0  0  1  0
       1 |  0 |  0  1  0  0
       1 |  1 |  1  0  0  0
          

Diagram:

[Diagram of 2 input lines connected to logic gates generating 4 outputs]

3. Encoder

An encoder performs the reverse operation of a decoder. It converts 2ⁿ inputs into n output lines.

Example: 4-to-2 Encoder

      Inputs: D0 to D3
      Outputs: A0, A1
      
      A1 = D2 + D3
      A0 = D1 + D3
          

Truth Table:

      D3 | D2 | D1 | D0 | A1 A0
      -------------------------
       0 |  0 |  0 |  1 |  0  0
       0 |  0 |  1 |  0 |  0  1
       0 |  1 |  0 |  0 |  1  0
       1 |  0 |  0 |  0 |  1  1
          

Diagram:

[Logic gate connections converting 4 input lines to 2 output lines]

4. Adder

An adder circuit adds binary numbers. Two types: Half Adder and Full Adder.

4.1 Half Adder

      Inputs: A, B
      Sum = A ⊕ B
      Carry = A ⋅ B
          
      A | B | Sum | Carry
      -------------------
      0 | 0 |  0  |   0
      0 | 1 |  1  |   0
      1 | 0 |  1  |   0
      1 | 1 |  0  |   1
          

4.2 Full Adder

      Inputs: A, B, Cin
      Sum = A ⊕ B ⊕ Cin
      Carry = (A ⋅ B) + (B ⋅ Cin) + (A ⋅ Cin)
          

Truth Table:

      A | B | Cin | Sum | Carry
      -------------------------
      0 | 0 |  0  |  0  |  0
      0 | 1 |  0  |  1  |  0
      1 | 0 |  0  |  1  |  0
      1 | 1 |  0  |  0  |  1
      0 | 0 |  1  |  1  |  0
      0 | 1 |  1  |  0  |  1
      1 | 0 |  1  |  0  |  1
      1 | 1 |  1  |  1  |  1
          

Diagram:

[Full adder circuit using two half adders and OR gate]

5. Subtractor

A subtractor circuit subtracts binary numbers. Two types: Half Subtractor and Full Subtractor.

5.1 Half Subtractor

      Inputs: A, B
      Difference = A ⊕ B
      Borrow = A' ⋅ B
          

Truth Table:

      A | B | Diff | Borrow
      ---------------------
      0 | 0 |  0   |   0
      0 | 1 |  1   |   1
      1 | 0 |  1   |   0
      1 | 1 |  0   |   0
          

5.2 Full Subtractor

      Inputs: A, B, Bin
      Difference = A ⊕ B ⊕ Bin
      Borrow = A' ⋅ B + (A' ⊕ B) ⋅ Bin
          

Truth Table:

      A | B | Bin | Diff | Borrow
      ---------------------------
      0 | 0 |  0  |  0   |   0
      0 | 1 |  0  |  1   |   1
      1 | 0 |  0  |  1   |   0
      1 | 1 |  0  |  0   |   0
      0 | 0 |  1  |  1   |   1
      0 | 1 |  1  |  0   |   1
      1 | 0 |  1  |  0   |   0
      1 | 1 |  1  |  1   |   1
          

Diagram:

[Full subtractor using two half subtractors and OR gate]

UNIT-III: Memories

1. ROM (Read Only Memory)

ROM is non-volatile memory used to store firmware or permanent data that doesn't change frequently.

Characteristics:

Used In: BIOS, embedded systems, calculators.

Diagram: [Block diagram showing address lines → ROM → Data Output]

2. PROM (Programmable ROM)

PROM is a type of ROM that can be programmed once by the user after manufacturing.

Characteristics:

Diagram: [PROM chip with programming fuses shown]

3. EPROM (Erasable Programmable ROM)

EPROM can be erased using ultraviolet light and reprogrammed.

Characteristics:

Diagram: [EPROM with quartz window shown]

4. RAM (Random Access Memory)

RAM is volatile memory used for temporary data storage while programs are running.

Types:

Characteristics:

Diagram: [RAM block with address, data lines and control lines]

5. Hard Disk

A hard disk is a magnetic storage device used for storing OS, software, files, etc.

Characteristics:

Diagram: [Platter, spindle, actuator arm, read/write head]

6. Floppy Disk

A floppy disk is an older magnetic storage device used for small data transfer and backup.

Characteristics:

Diagram: [Circular disk inside plastic casing with magnetic coating]

7. CD-ROM (Compact Disc - Read Only Memory)

CD-ROMs are optical disks used for storing music, software, and other read-only data.

Characteristics:

Diagram: [Laser lens reading circular track on CD surface]

UNIT-IV: Sequential Building Blocks

1. Flip-Flop

Flip-flops are fundamental building blocks in digital electronics used to store binary data. A flip-flop is a bistable multivibrator with two stable states, used for storing one bit of information.

Types of Flip-Flops:

1. RS Flip-Flop (Reset-Set)

RS flip-flop has two inputs: R (reset) and S (set). The output changes based on the input combination.

Truth Table:

R S Q Q'
0 0 Previous State Previous State
0 1 1 0
1 0 0 1
1 1 Invalid Invalid

Diagram: [RS Flip-Flop symbol with reset and set inputs]

2. D Flip-Flop (Data Flip-Flop)

The D flip-flop is a modified version of the RS flip-flop, which eliminates the invalid state. It has a single input: D (data), and the output follows the value of the data input.

Truth Table:

D Q Q'
0 0 1
1 1 0

Diagram: [D Flip-Flop symbol with data input and Q output]

3. JK Flip-Flop

The JK flip-flop is a more versatile flip-flop. It has two inputs: J and K. It combines the functionality of the RS flip-flop and adds the ability to toggle the output.

Truth Table:

J K Q Q'
0 0 Previous State Previous State
0 1 0 1
1 0 1 0
1 1 Toggled Toggled

Diagram: [JK Flip-Flop symbol with J and K inputs]

4. Master-Slave Flip-Flop

Master-slave flip-flops are designed using two flip-flops connected in series, where the master flip-flop captures the input and the slave flip-flop holds the output, preventing race conditions.

Diagram: [Master-Slave Flip-Flop symbol with inputs and outputs]

5. T Flip-Flop (Toggle Flip-Flop)

The T flip-flop changes its state (toggles) with each clock pulse when the input T is high (1).

Truth Table:

T Q Q'
0 Previous State Previous State
1 Toggled Toggled

Diagram: [T Flip-Flop symbol with T input and Q output]

2. Registers & Shift Registers

Registers are used to store multiple bits of data in a digital system. A shift register is a type of register used for shifting data in or out of the register, usually used in data transmission and storage applications.

Shift Register Types:

Diagram: [Shift Register symbol showing input, clock, output]

3. Counters

Counters are sequential circuits used to count events or clock pulses. They can be asynchronous or synchronous.

Types of Counters:

Example: 4-bit Synchronous Counter using JK Flip-Flops

Diagram: [Synchronous counter circuit with JK flip-flops]

4. Synchronous vs Asynchronous Designing Method

The design methods of digital circuits are classified as synchronous and asynchronous:

Synchronous Design:

Asynchronous Design:

Diagram: [Synchronous and Asynchronous block diagrams]

UNIT-V: Memory Organization

1. Basic Cell of Static and Dynamic RAM

Memory in digital systems can be categorized into two primary types: Static RAM (SRAM) and Dynamic RAM (DRAM). Both are used for storing data but have different structures and properties.

1.1 Static RAM (SRAM)

SRAM uses bistable latches (flip-flops) to store data. The data is retained as long as the power is supplied, making it faster but more expensive compared to DRAM.

Basic Cell: A typical SRAM cell consists of four to six transistors forming a flip-flop that stores each bit of data.

Diagram: [SRAM cell diagram with 4 transistors]

1.2 Dynamic RAM (DRAM)

DRAM stores each bit of data in a capacitor, which must be periodically refreshed to maintain the stored data. DRAM is slower than SRAM but cheaper and more dense, making it suitable for larger memory systems.

Basic Cell: A DRAM cell consists of one transistor and one capacitor for each bit of data.

Diagram: [DRAM cell diagram with a single transistor and capacitor]

2. Building Large Memories Using Chips

Large memory systems are built by connecting multiple memory chips in parallel or series. Memory is typically organized in rows and columns, allowing for the selection of individual bits in a large memory space.

2.1 Memory Addressing

To address large memories, a memory controller is used to select rows and columns. Each memory chip has a specific address range, and the controller maps the address to the correct chip and location.

Diagram: [Memory chip addressing with multiple chips in parallel]

2.2 Chip Selection

Memory chips can be selected using address lines and chip-select signals. The memory controller sends the appropriate signals to select the correct chip based on the address provided by the CPU.

Diagram: [Block diagram of chip selection and memory organization]

3. Associative Memory

Associative memory, also known as content-addressable memory (CAM), is a type of memory that allows data to be accessed based on content rather than its address. In CAM, data is compared to a stored value, and if a match is found, the corresponding data is retrieved.

3.1 Functionality of CAM

CAM consists of memory cells where each cell has a comparator that compares the input with the stored data. If a match is found, the address of the matching data is output.

Diagram: [Block diagram showing a CAM cell with comparator and address lines]

4. Cache Memory Organization

Cache memory is a small, high-speed memory that stores frequently accessed data. It acts as a buffer between the CPU and main memory, reducing the average time to access data from the main memory.

4.1 Cache Levels

4.2 Cache Mapping Techniques

Diagram: [Cache memory organization with L1, L2, and L3 caches]

5. Virtual Memory Organization

Virtual memory is a technique that uses a portion of the hard disk as an extension of RAM, allowing programs to use more memory than is physically available. Virtual memory is managed by the operating system using a page table that maps virtual addresses to physical addresses in RAM.

5.1 Page Tables

Page tables are used to map virtual addresses to physical addresses. Each page in virtual memory corresponds to a block in physical memory. The operating system manages page tables and performs paging to transfer data between RAM and the hard disk when needed.

Diagram: [Page table diagram showing virtual and physical address mapping]

5.2 Page Faults

A page fault occurs when a program accesses a page that is not currently in physical memory. When this happens, the operating system must load the page from the hard disk into RAM, causing a delay in execution.

Diagram: [Page fault flowchart showing the steps of handling a page fault]